This invention relates to a method of designing dummy wiring in a semiconductor device, and more particularly to a method of designing dummy wiring used to improve the flatness of an insulating film deposited on a region in which underlayer wiring exists.
In the manufacture of Ultra Large Scale Integrated (ULSI) Circuits, it is well known that the series of process steps of forming a deposit film such as an insulating film on a semiconductor substrate, and forming a fine pattern such as a wiring pattern on the deposit film are repeated.
The process of forming a fine pattern includes two steps--a photolithography step and an etching step.
In the photolithography step, a to-be-patterned film such as a metal film is coated with a photoresist (a coating step), and then a mask is provided on the photoresist and predetermined regions of the photoresist are radiated with light (an exposure step).
After the exposure step, the photoresist is processed using a developer as in the case of the development of a photograph. Those regions of the photoresist which are radiated with light are chemically changed. Those chemically changed regions can be removed using the developer.
Thus, a photoresist pattern which is the same pattern as the mask pattern is formed.
In the etching step, the resultant photoresist pattern is used as a mask, thereby etching a film, which is usually patterned by RIE (Reactive Ion Etching), into the same pattern as the photoresist pattern.
However, the method of forming a fine pattern using photolithography is more and more complicated and difficult to carry out, for the following reasons:
(1) The size of the pattern to be formed is decreasing. The minimum size of the presently manufactured ULSIs is less than 0.5 .mu.m.
(2) In accordance with the increase of the degree of integration, i.e. the increase of the number of elements such as transistors integrated in a single chip, the required length of the entire wiring used to connect the elements is increasing rapidly. This means that the number of layers for multi-layer wiring must be increased to avoid an increase in chip size.
The conventional multi-layer wiring is formed as below.
First, a first wire layer is formed using the above-mentioned fine pattern forming method.
Then, an interlayer insulating film is formed on the first wire layer, and a via hole is formed in the interlayer insulating film (a first step).
Subsequently, a plug is formed in the via hole, and a second wire layer to be connected to the first wire layer by means of the plug is formed using the fine pattern forming method (a second step).
After that, the first and second steps are repeated, thereby forming multi-layer wiring of a predetermined number of layers.
The above-described multi-layer wiring formation method has the following problems:
As is shown in FIG. 7, the multi-layer wiring forming method includes the step of forming an interlayer insulating film 82 which covers wiring 81. As is evident from the figure, the interlayer insulating film 82 has an uneven surface which reflects the pattern of the underlayer wiring 81.
Where the interlayer insulating film 82 with the uneven surface is coated with a resist and then subjected to photolithography, light to be used for exposure must have a greater focal depth than in the case of an interlayer insulating film of a flat surface.
On the other hand, it is necessary, in photolithography, to enhance the resolution of exposing light using short wavelength light in order to selectively expose fine regions. However, the greater the resolution, the shallower the focal depth. Accordingly, it is difficult to form a desired fine pattern on the interlayer insulating film 82 with the uneven surface.
This problem can be solved by flattening the surface of the interlayer insulating film. Among the flattening techniques, CMP (Chemical Mechanical Polishing) has been being used widely since it can flatten the entire wafer with high precision.
CMP, however, will cause a "dishing" phenomenon which is a well-known problem. This phenomenon occurs due to variations in the density of wiring 81 located under the interlayer insulating film 82. As is shown in FIGS. 8A and 8B, the amount of polishing is greater in a region of a low wiring density in which no wiring 81 exist, than in the other region of a high wiring density in which the wiring 81 exists. As a result, the level of the surface of that portion of the interlayer insulating film 82, which is provided on the region of the low wiring density, is lower than the level of the surface of that portion of the film 82 which is provided on the are of the high wiring density.
Thus, that part of the film 82 which has a high wiring density underneath shows a high degree of flatness but the entire film 82 is not completely flat. This is especially disadvantageous in the case of a logic device in which wires are provided at random on the entire chip, i.e. the range of variations in wiring density may be large.
To prevent occurrence of dishing, it suffices if dummy wiring 83 is provided on a region in which dishing will occur, thereby minimizing the range of variations in wiring density, as is shown in FIGS. 9A and 9B.
In this case, it is necessary to precisely determine the region in which the dummy wiring 83 is formed. In the conventional method of determining the region for the dummy wiring 83, first, the layout of the entire chip is inspected, then dummy wiring is actually provided on the region of the chip in which dishing may occur, and CMP is performed to determine whether or not dishing occurs in the region. The determination of the region in which dishing may occur, the formation of the dummy wiring, and CMP are repeated until dishing does not occur any more.
However, since, the above determinations are performed manually, the time required is very large.